********************************************************************************
**  Generating Lyx docs for VHDL entity interfaces!
********************************************************************************

 Python version is: python3.6 

{'template': '../doc/core/template.lyx', 'source_list': {'fault_confinement': {'vhdl_file': '../src/can_core/fault_confinement/fault_confinement.vhd', 'lyx_output': '../doc/core/entity_docs/fault_confinement.lyx'}, 'protocol_control': {'vhdl_file': '../src/can_core/protocol_control/protocol_control.vhd', 'lyx_output': '../doc/core/entity_docs/protocol_control.lyx'}, 'can_core': {'vhdl_file': '../src/can_core/can_core.vhd', 'lyx_output': '../doc/core/entity_docs/can_core.lyx'}, 'can_top_level': {'vhdl_file': '../src/can_top_level.vhd', 'lyx_output': '../doc/core/entity_docs/can_top_level.lyx'}, 'operation_control': {'vhdl_file': '../src/can_core/operation_control/operation_control.vhd', 'lyx_output': '../doc/core/entity_docs/operation_control.lyx'}, 'bit_stuffing': {'vhdl_file': '../src/can_core/bit_stuffing/bit_stuffing.vhd', 'lyx_output': '../doc/core/entity_docs/bit_stuffing.lyx'}, 'bit_destuffing': {'vhdl_file': '../src/can_core/bit_destuffing/bit_destuffing.vhd', 'lyx_output': '../doc/core/entity_docs/bit_destuffing.lyx'}, 'can_crc': {'vhdl_file': '../src/can_core/crc/can_crc.vhd', 'lyx_output': '../doc/core/entity_docs/can_crc.lyx'}, 'prescaler': {'vhdl_file': '../src/prescaler/prescaler.vhd', 'lyx_output': '../doc/core/entity_docs/prescaler.lyx'}, 'bus_sampling': {'vhdl_file': '../src/bus_sampling/bus_sampling.vhd', 'lyx_output': '../doc/core/entity_docs/bus_sampling.lyx'}}}
********************************************************************************
Processing fault_confinement entity
********************************************************************************
Moving to VhdlEntityParserState.ENTITY
Moving to VhdlEntityParserState.GENERICS
G_RESET_POLARITY
std_logic
'0'
Adding generic entry:  {'entry_type': 'generic', 'name': 'G_RESET_POLARITY', 'type': 'std_logic', 'comment': '', 'def_val': "'0'"}
Moving to VhdlEntityParserState.ENTITY
Moving to VhdlEntityParserState.PORTS
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Clock and Asynchronous Reset'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'clk_sys', 'type': 'std_logic', 'comment': 'System clock', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'res_n', 'type': 'std_logic', 'comment': 'Asynchronous reset', 'direction': 'in'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Memory registers interface'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'drv_bus', 'type': 'std_logic_vector (1023 downto 0)', 'comment': 'Driving Bus', 'direction': 'in'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Error signalling for interrupts'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'error_passive_changed', 'type': 'std_logic', 'comment': 'Error passive state changed', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'error_warning_limit', 'type': 'std_logic', 'comment': 'Error warning limit was reached', 'direction': 'out'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Operation control Interface'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'is_transmitter', 'type': 'std_logic', 'comment': 'Unit is transmitter', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'is_receiver', 'type': 'std_logic', 'comment': 'Unit is receiver', 'direction': 'in'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Protocol control Interface'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'sp_control', 'type': 'std_logic_vector (1 downto 0)', 'comment': 'Sample control (Nominal, Data, Secondary)', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'set_err_active', 'type': 'std_logic', 'comment': 'Set unit to error active (after re-integration). Erases erorcounters to 0!', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'err_detected', 'type': 'std_logic', 'comment': 'Error is detected', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'err_ctrs_unchanged', 'type': 'std_logic', 'comment': 'Error counter should remain unchanged', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'primary_error', 'type': 'std_logic', 'comment': 'Primary Error', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'act_err_ovr_flag', 'type': 'std_logic', 'comment': 'Active Error Flag or Overload flag is being tranmsmitted', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'err_delim_late', 'type': 'std_logic', 'comment': 'Error delimiter too late', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'tran_valid', 'type': 'std_logic', 'comment': 'Transmission of frame valid', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'rec_valid', 'type': 'std_logic', 'comment': 'Reception of frame valid', 'direction': 'in'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Fault confinement State indication'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'is_err_active', 'type': 'std_logic', 'comment': 'Unit is error active', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'is_err_passive', 'type': 'std_logic', 'comment': 'Unit is error passive', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'is_bus_off', 'type': 'std_logic', 'comment': 'Unit is Bus-off', 'direction': 'out'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Error counters'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'tx_err_ctr', 'type': 'std_logic_vector (8 downto 0)', 'comment': 'TX Error counter', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'rx_err_ctr', 'type': 'std_logic_vector (8 downto 0)', 'comment': 'RX Error counter', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'norm_err_ctr', 'type': 'std_logic_vector (15 downto 0)', 'comment': 'Error counter in Nominal Bit-rate', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'data_err_ctr', 'type': 'std_logic_vector (15 downto 0)', 'comment': 'Error counter in Data Bit-rate', 'direction': 'out'}
Moving to VhdlEntityParserState.ENTITY
Moving to VhdlEntityParserState.FINISH
********************************************************************************
Processing protocol_control entity
********************************************************************************
Moving to VhdlEntityParserState.ENTITY
Moving to VhdlEntityParserState.GENERICS
G_RESET_POLARITY
std_logic
'0'
Adding generic entry:  {'entry_type': 'generic', 'name': 'G_RESET_POLARITY', 'type': 'std_logic', 'comment': 'Reset polarity', 'def_val': "'0'"}
G_CTRL_CTR_WIDTH
natural
9
Adding generic entry:  {'entry_type': 'generic', 'name': 'G_CTRL_CTR_WIDTH', 'type': 'natural', 'comment': 'Control counter width', 'def_val': '9'}
G_RETR_LIM_CTR_WIDTH
natural
4
Adding generic entry:  {'entry_type': 'generic', 'name': 'G_RETR_LIM_CTR_WIDTH', 'type': 'natural', 'comment': 'Retransmitt limit counter width', 'def_val': '4'}
G_ERR_VALID_PIPELINE
boolean
true
Adding generic entry:  {'entry_type': 'generic', 'name': 'G_ERR_VALID_PIPELINE', 'type': 'boolean', 'comment': 'Insert pipeline on "error_valid"', 'def_val': 'true'}
Moving to VhdlEntityParserState.ENTITY
Moving to VhdlEntityParserState.PORTS
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Clock and Asynchronous Reset'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'clk_sys', 'type': 'std_logic', 'comment': 'System clock', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'res_n', 'type': 'std_logic', 'comment': 'Asynchronous reset', 'direction': 'in'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Memory registers interface'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'drv_bus', 'type': 'std_logic_vector (1023 downto 0)', 'comment': 'Driving bus', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'alc', 'type': 'std_logic_vector (7 downto 0)', 'comment': 'Arbitration lost capture', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'erc_capture', 'type': 'std_logic_vector (7 downto 0)', 'comment': 'Error code capture', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'is_arbitration', 'type': 'std_logic', 'comment': 'Arbitration field is being transmitted', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'is_control', 'type': 'std_logic', 'comment': 'Control field is being transmitted', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'is_data', 'type': 'std_logic', 'comment': 'Data field is being transmitted', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'is_stuff_count', 'type': 'std_logic', 'comment': 'Stuff Count field is being transmitted', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'is_crc', 'type': 'std_logic', 'comment': 'CRC field is being transmitted', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'is_crc_delim', 'type': 'std_logic', 'comment': 'CRC Delimiter is being transmitted', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'is_ack_field', 'type': 'std_logic', 'comment': 'ACK field is being transmitted', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'is_ack_delim', 'type': 'std_logic', 'comment': 'ACK Delimiter is being transmitted', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'is_eof', 'type': 'std_logic', 'comment': 'End of Frame field is being transmitted', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'is_intermission', 'type': 'std_logic', 'comment': 'Intermission is being transmitted', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'is_suspend', 'type': 'std_logic', 'comment': 'Suspend transmission is being transmitted', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'is_error', 'type': 'std_logic', 'comment': 'Error frame is being transmitted', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'is_overload', 'type': 'std_logic', 'comment': 'Overload frame is being transmitted', 'direction': 'out'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'TXT Buffers interface'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'tran_word', 'type': 'std_logic_vector (31 downto 0)', 'comment': 'TX Data word', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'tran_dlc', 'type': 'std_logic_vector (3 downto 0)', 'comment': 'TX Data length code', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'tran_is_rtr', 'type': 'std_logic', 'comment': 'TX Remote transmission request flag', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'tran_ident_type', 'type': 'std_logic', 'comment': 'TX Identifier type (0-Basic, 1-Extended)', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'tran_frame_type', 'type': 'std_logic', 'comment': 'TX Frame type (0-CAN 2.0, 1-CAN FD)', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'tran_brs', 'type': 'std_logic', 'comment': 'TX Bit rate shift', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'tran_frame_valid', 'type': 'std_logic', 'comment': 'Frame in TXT Buffer is valid any can be transmitted.', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'txtb_hw_cmd', 'type': 't_txtb_hw_cmd', 'comment': 'HW Commands for TX Arbitrator and TXT Buffers', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'txtb_ptr', 'type': 'natural range 0 to 19', 'comment': 'Pointer to TXT buffer memory', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'txtb_changed', 'type': 'std_logic', 'comment': 'Selected TXT Buffer index changed', 'direction': 'in'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'RX Buffer interface'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'rec_ident', 'type': 'std_logic_vector (28 downto 0)', 'comment': 'RX CAN Identifier', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'rec_dlc', 'type': 'std_logic_vector (3 downto 0)', 'comment': 'RX Data length code', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'rec_is_rtr', 'type': 'std_logic', 'comment': 'RX Remote transmission request flag', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'rec_ident_type', 'type': 'std_logic', 'comment': 'RX Recieved identifier type (0-BASE Format, 1-Extended Format);', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'rec_frame_type', 'type': 'std_logic', 'comment': 'RX frame type (0-CAN 2.0, 1- CAN FD)', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'rec_brs', 'type': 'std_logic', 'comment': 'RX Bit rate shift Flag', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'rec_esi', 'type': 'std_logic', 'comment': 'RX Error state indicator', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'store_metadata', 'type': 'std_logic', 'comment': 'Store Metadata in RX Buffer', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'rec_abort', 'type': 'std_logic', 'comment': 'Abort storing of frame in RX Buffer. Revert to last frame.', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'store_data', 'type': 'std_logic', 'comment': 'Store data word to RX Buffer.', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'store_data_word', 'type': 'std_logic_vector (31 downto 0)', 'comment': 'Data words to be stored to RX Buffer.', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'sof_pulse', 'type': 'std_logic', 'comment': 'Pulse in Start of Frame', 'direction': 'out'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Operation control FSM Interface'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'is_transmitter', 'type': 'std_logic', 'comment': 'Unit is transmitter', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'is_receiver', 'type': 'std_logic', 'comment': 'Unit is receiver', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'is_idle', 'type': 'std_logic', 'comment': 'Unit is idle', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'arbitration_lost', 'type': 'std_logic', 'comment': 'Loss of arbitration -> Turn receiver!', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'set_transmitter', 'type': 'std_logic', 'comment': 'Set unit to be transmitter (in SOF)', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'set_receiver', 'type': 'std_logic', 'comment': 'Set unit to be receiver', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'set_idle', 'type': 'std_logic', 'comment': 'Set unit to be idle', 'direction': 'out'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Fault confinement Interface'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'is_err_active', 'type': 'std_logic', 'comment': 'Unit is error active', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'is_err_passive', 'type': 'std_logic', 'comment': 'Unit is error passive', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'is_bus_off', 'type': 'std_logic', 'comment': 'Unit is Bus-off', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'err_detected', 'type': 'std_logic', 'comment': 'Error detected', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'primary_error', 'type': 'std_logic', 'comment': 'Primary Error', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'act_err_ovr_flag', 'type': 'std_logic', 'comment': 'Active Error or Overload flag is being tranmsmitted', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'err_delim_late', 'type': 'std_logic', 'comment': 'Error delimiter too late', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'set_err_active', 'type': 'std_logic', 'comment': 'Set unit to be error active', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'err_ctrs_unchanged', 'type': 'std_logic', 'comment': 'Error counters should remain unchanged', 'direction': 'out'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'TX and RX Trigger signals to Sample and Transmitt Data'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'tx_trigger', 'type': 'std_logic', 'comment': 'TX Trigger (in SYNC segment)', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'rx_trigger', 'type': 'std_logic', 'comment': 'RX Trigger (one clock cycle delayed after Sample point)', 'direction': 'in'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'CAN Bus serial data stream'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'tx_data_nbs', 'type': 'std_logic', 'comment': 'TX Data', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'tx_data_wbs', 'type': 'std_logic', 'comment': 'TX Data (post bit stuffing)', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'rx_data_nbs', 'type': 'std_logic', 'comment': 'RX Data', 'direction': 'in'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Bit Stuffing Interface'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'stuff_enable', 'type': 'std_logic', 'comment': 'Bit Stuffing enabled', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'destuff_enable', 'type': 'std_logic', 'comment': 'Bit De-stuffing enabled', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'fixed_stuff', 'type': 'std_logic', 'comment': 'Bit Stuffing type (0-Normal, 1-Fixed)', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'stuff_length', 'type': 'std_logic_vector (2 downto 0)', 'comment': 'Length of Bit Stuffing rule', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'stuff_error_enable', 'type': 'std_logic', 'comment': 'Enable detection of Stuff Error', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'dst_ctr', 'type': 'natural range 0 to 7', 'comment': 'Number of de-stuffed bits modulo 8', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'bst_ctr', 'type': 'natural range 0 to 7', 'comment': 'Number of stuffed bits modulo 8', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'stuff_error', 'type': 'std_logic', 'comment': 'Stuff Error', 'direction': 'in'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Bus Sampling Interface'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'bit_error', 'type': 'std_logic', 'comment': 'Bit Error detected', 'direction': 'in'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'CRC Interface'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'crc_enable', 'type': 'std_logic', 'comment': 'Enable CRC calculation', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'crc_spec_enable', 'type': 'std_logic', 'comment': 'CRC calculation - speculative enable', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'crc_src', 'type': 'std_logic_vector (1 downto 0)', 'comment': 'CRC Source to be used (CRC 15, CRC 17, CRC 21)', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'crc_15', 'type': 'std_logic_vector (14 downto 0)', 'comment': 'Calculated CRC 15', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'crc_17', 'type': 'std_logic_vector (16 downto 0)', 'comment': 'Calculated CRC 17', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'crc_21', 'type': 'std_logic_vector (20 downto 0)', 'comment': 'Calculated CRC 21', 'direction': 'in'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Control signals'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'sp_control', 'type': 'std_logic_vector (1 downto 0)', 'comment': 'Sample control (Nominal, Data, Secondary)', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'sync_control', 'type': 'std_logic_vector (1 downto 0)', 'comment': 'Synchronisation control (No synchronisation, Hard Synchronisation,Resynchronisation', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'no_pos_resync', 'type': 'std_logic', 'comment': 'No Resynchronisation due to positive phase error', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'ssp_reset', 'type': 'std_logic', 'comment': 'Clear the Shift register for secondary sampling point.', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'trv_delay_calib', 'type': 'std_logic', 'comment': 'Enable measurement of Transciever delay', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'tran_valid', 'type': 'std_logic', 'comment': 'Transmitted frame is valid', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'rec_valid', 'type': 'std_logic', 'comment': 'Received frame is valid', 'direction': 'out'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Status signals'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'ack_received', 'type': 'std_logic', 'comment': 'ACK received', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'br_shifted', 'type': 'std_logic', 'comment': 'Bit rate shifted', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'form_error', 'type': 'std_logic', 'comment': 'Form Error has occurred', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'ack_error', 'type': 'std_logic', 'comment': 'ACK Error has occurred', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'crc_error', 'type': 'std_logic', 'comment': 'CRC Error has occurred', 'direction': 'out'}
Moving to VhdlEntityParserState.ENTITY
Moving to VhdlEntityParserState.FINISH
********************************************************************************
Processing can_core entity
********************************************************************************
Moving to VhdlEntityParserState.ENTITY
Moving to VhdlEntityParserState.GENERICS
G_RESET_POLARITY
std_logic
'0'
Adding generic entry:  {'entry_type': 'generic', 'name': 'G_RESET_POLARITY', 'type': 'std_logic', 'comment': 'Reset polarity', 'def_val': "'0'"}
G_SAMPLE_TRIGGER_COUNT
natural range 2 to 8
2
Adding generic entry:  {'entry_type': 'generic', 'name': 'G_SAMPLE_TRIGGER_COUNT', 'type': 'natural range 2 to 8', 'comment': 'Number of signals in Sample trigger', 'def_val': '2'}
G_CTRL_CTR_WIDTH
natural
9
Adding generic entry:  {'entry_type': 'generic', 'name': 'G_CTRL_CTR_WIDTH', 'type': 'natural', 'comment': 'Control counter width', 'def_val': '9'}
G_RETR_LIM_CTR_WIDTH
natural
4
Adding generic entry:  {'entry_type': 'generic', 'name': 'G_RETR_LIM_CTR_WIDTH', 'type': 'natural', 'comment': 'Retransmitt limit counter width', 'def_val': '4'}
G_ERR_VALID_PIPELINE
boolean
true
Adding generic entry:  {'entry_type': 'generic', 'name': 'G_ERR_VALID_PIPELINE', 'type': 'boolean', 'comment': 'Insert pipeline on "error_valid"', 'def_val': 'true'}
G_CRC15_POL
std_logic_vector
x"C599"
Adding generic entry:  {'entry_type': 'generic', 'name': 'G_CRC15_POL', 'type': 'std_logic_vector', 'comment': 'CRC 15 polynomial', 'def_val': 'x"C599"'}
G_CRC17_POL
std_logic_vector
x"3685B"
Adding generic entry:  {'entry_type': 'generic', 'name': 'G_CRC17_POL', 'type': 'std_logic_vector', 'comment': 'CRC 17 polynomial', 'def_val': 'x"3685B"'}
G_CRC21_POL
std_logic_vector
x"302899"
Adding generic entry:  {'entry_type': 'generic', 'name': 'G_CRC21_POL', 'type': 'std_logic_vector', 'comment': 'CRC 15 polynomial', 'def_val': 'x"302899"'}
Moving to VhdlEntityParserState.ENTITY
Moving to VhdlEntityParserState.PORTS
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Clock and Asynchronous reset'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'clk_sys', 'type': 'std_logic', 'comment': 'System clock', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'res_n', 'type': 'std_logic', 'comment': 'Asynchronous reset', 'direction': 'in'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Memory registers interface'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'drv_bus', 'type': 'std_logic_vector (1023 downto 0)', 'comment': 'Driving bus', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'stat_bus', 'type': 'std_logic_vector (511 downto 0)', 'comment': 'Status bus', 'direction': 'out'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Tx Arbitrator and TXT Buffers interface'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'tran_word', 'type': 'std_logic_vector (31 downto 0)', 'comment': 'TX Data word', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'tran_dlc', 'type': 'std_logic_vector (3 downto 0)', 'comment': 'TX Data length code', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'tran_is_rtr', 'type': 'std_logic', 'comment': 'TX Remote transmission request flag', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'tran_ident_type', 'type': 'std_logic', 'comment': 'TX Identifier type (0-Basic, 1-Extended)', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'tran_frame_type', 'type': 'std_logic', 'comment': 'TX Frame type (0-CAN 2.0, 1-CAN FD)', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'tran_brs', 'type': 'std_logic', 'comment': 'TX Bit Rate Shift', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'tran_frame_valid', 'type': 'std_logic', 'comment': 'Frame in TXT Buffer is valid any can be transmitted.', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'txtb_hw_cmd', 'type': 't_txtb_hw_cmd', 'comment': 'HW Commands for TX Arbitrator and TXT Buffers', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'txtb_changed', 'type': 'std_logic', 'comment': 'Selected TXT Buffer index changed', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'txtb_ptr', 'type': 'natural range 0 to 19', 'comment': 'Pointer to TXT buffer memory', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'is_bus_off', 'type': 'std_logic', 'comment': 'Transition to bus off has occurred', 'direction': 'out'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Recieve Buffer and Message Filter Interface'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'rec_ident', 'type': 'std_logic_vector (28 downto 0)', 'comment': 'RX CAN Identifier', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'rec_dlc', 'type': 'std_logic_vector (3 downto 0)', 'comment': 'RX Data length code', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'rec_ident_type', 'type': 'std_logic', 'comment': 'RX Recieved identifier type (0-BASE Format, 1-Extended Format);', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'rec_frame_type', 'type': 'std_logic', 'comment': 'RX frame type (0-CAN 2.0, 1- CAN FD)', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'rec_is_rtr', 'type': 'std_logic', 'comment': 'RX Remote transmission request Flag', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'rec_brs', 'type': 'std_logic', 'comment': 'RX Bit Rate Shift bit', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'rec_esi      \t', 'type': 'std_logic', 'comment': 'RX Error state indicator', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'rec_valid', 'type': 'std_logic', 'comment': 'RX Frame received succesfully, can be commited to RX Buffer.', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'store_metadata', 'type': 'std_logic', 'comment': 'Metadata are received OK, and can be stored in RX Buffer.', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'store_data', 'type': 'std_logic', 'comment': 'Store data word to RX Buffer.', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'store_data_word', 'type': 'std_logic_vector (31 downto 0)', 'comment': 'Data words to be stored to RX Buffer.', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'rec_abort', 'type': 'std_logic', 'comment': 'Abort storing of frame in RX Buffer. Revert to last frame.', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'sof_pulse', 'type': 'std_logic', 'comment': 'Pulse in Start of Frame', 'direction': 'out'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Interrupt Manager Interface'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'arbitration_lost', 'type': 'std_logic', 'comment': 'Arbitration was lost', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'tran_valid', 'type': 'std_logic', 'comment': 'Frame stored in CAN Core was sucessfully transmitted', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'br_shifted', 'type': 'std_logic', 'comment': 'Bit Rate Was Shifted', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'err_detected', 'type': 'std_logic', 'comment': 'Error is detected (Error frame will be transmitted)', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'error_passive_changed', 'type': 'std_logic', 'comment': 'Error passive state changed', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'error_warning_limit', 'type': 'std_logic', 'comment': 'Error warning limit reached', 'direction': 'out'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Prescaler interface'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'rx_triggers', 'type': 'std_logic_vector (G_SAMPLE_TRIGGER_COUNT - 1 downto 0)', 'comment': 'RX Triggers (in Sample Point)', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'tx_trigger', 'type': 'std_logic', 'comment': 'TX Trigger', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'sync_control', 'type': 'std_logic_vector (1 downto 0)', 'comment': 'Synchronisation control (No synchronisation, Hard Synchronisation,Resynchronisation', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'no_pos_resync', 'type': 'std_logic', 'comment': 'No positive resynchronisation', 'direction': 'out'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'CAN Bus serial data stream'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'rx_data_wbs', 'type': 'std_logic', 'comment': 'RX Data from CAN Bus', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'tx_data_wbs', 'type': 'std_logic', 'comment': 'TX Data to CAN Bus', 'direction': 'out'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Others'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'timestamp', 'type': 'std_logic_vector (63 downto 0)', 'comment': '', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'sp_control', 'type': 'std_logic_vector (1 downto 0)', 'comment': 'Sample control (Nominal, Data, Secondary)', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'ssp_reset', 'type': 'std_logic', 'comment': 'Secondary sample point reset', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'trv_delay_calib', 'type': 'std_logic', 'comment': 'Enable measurement of Transciever delay', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'bit_error', 'type': 'std_logic', 'comment': 'Bit Error detected', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'sample_sec', 'type': 'std_logic', 'comment': 'Secondary sample signal', 'direction': 'in'}
Moving to VhdlEntityParserState.ENTITY
Moving to VhdlEntityParserState.FINISH
********************************************************************************
Processing can_top_level entity
********************************************************************************
Moving to VhdlEntityParserState.ENTITY
Moving to VhdlEntityParserState.GENERICS
rx_buffer_size
natural range 32 to 4096
128
Adding generic entry:  {'entry_type': 'generic', 'name': 'rx_buffer_size', 'type': 'natural range 32 to 4096', 'comment': 'RX Buffer RAM size (32 bit words)', 'def_val': '128'}
ID
natural range 0 to 15
1
Adding generic entry:  {'entry_type': 'generic', 'name': 'ID', 'type': 'natural range 0 to 15', 'comment': 'ID (bits 19-16 of adress)', 'def_val': '1'}
sup_filtA
boolean
true
Adding generic entry:  {'entry_type': 'generic', 'name': 'sup_filtA', 'type': 'boolean', 'comment': 'Insert Filter A', 'def_val': 'true'}
sup_filtB
boolean
true
Adding generic entry:  {'entry_type': 'generic', 'name': 'sup_filtB', 'type': 'boolean', 'comment': 'Insert Filter B', 'def_val': 'true'}
sup_filtC
boolean
true
Adding generic entry:  {'entry_type': 'generic', 'name': 'sup_filtC', 'type': 'boolean', 'comment': 'Insert Filter C', 'def_val': 'true'}
sup_range
boolean
true
Adding generic entry:  {'entry_type': 'generic', 'name': 'sup_range', 'type': 'boolean', 'comment': 'Insert Range Filter', 'def_val': 'true'}
Moving to VhdlEntityParserState.ENTITY
Moving to VhdlEntityParserState.PORTS
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Clock and Asynchronous reset'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'clk_sys', 'type': 'in std_logic', 'comment': 'System clock', 'direction': ''}
Adding port entry:  {'entry_type': 'port', 'name': 'res_n', 'type': 'in std_logic', 'comment': 'Asynchronous reset', 'direction': ''}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Memory interface'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'data_in', 'type': 'in  std_logic_vector (31 downto 0)', 'comment': 'Input data', 'direction': ''}
Adding port entry:  {'entry_type': 'port', 'name': 'data_out', 'type': 'out std_logic_vector (31 downto 0)', 'comment': 'Output data', 'direction': ''}
Adding port entry:  {'entry_type': 'port', 'name': 'adress', 'type': 'in  std_logic_vector (15 downto 0)', 'comment': 'Address', 'direction': ''}
Adding port entry:  {'entry_type': 'port', 'name': 'scs', 'type': 'in  std_logic', 'comment': 'Chip select', 'direction': ''}
Adding port entry:  {'entry_type': 'port', 'name': 'srd', 'type': 'in  std_logic', 'comment': 'Read indication', 'direction': ''}
Adding port entry:  {'entry_type': 'port', 'name': 'swr', 'type': 'in  std_logic', 'comment': 'Write indication', 'direction': ''}
Adding port entry:  {'entry_type': 'port', 'name': 'sbe', 'type': 'in  std_logic_vector (3 downto 0)', 'comment': 'Byte enable', 'direction': ''}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Interrupt Interface'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'int', 'type': 'out std_logic', 'comment': 'Interrupt output', 'direction': ''}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'CAN Bus Interface'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'can_tx', 'type': 'out std_logic', 'comment': 'TX signal to CAN bus', 'direction': ''}
Adding port entry:  {'entry_type': 'port', 'name': 'can_rx', 'type': 'in  std_logic', 'comment': 'RX signal from CAN bus', 'direction': ''}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Synchronisation signals'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'time_quanta_clk', 'type': 'out std_logic', 'comment': 'Time Quanta clocks', 'direction': ''}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Internal signals for testbenches'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'drv_bus_o', 'type': 'out std_logic_vector (1023 downto 0)', 'comment': 'synthesis translate_offDriving Bus output', 'direction': ''}
Adding port entry:  {'entry_type': 'port', 'name': 'stat_bus_o', 'type': 'out std_logic_vector (511 downto 0)', 'comment': 'Status Bus output', 'direction': ''}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Timestamp for time based transmission / reception'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'timestamp', 'type': 'in std_logic_vector (63 downto 0)', 'comment': '', 'direction': ''}
Moving to VhdlEntityParserState.ENTITY
********************************************************************************
Processing operation_control entity
********************************************************************************
Moving to VhdlEntityParserState.ENTITY
Moving to VhdlEntityParserState.GENERICS
G_RESET_POLARITY
std_logic

Adding generic entry:  {'entry_type': 'generic', 'name': 'G_RESET_POLARITY', 'type': 'std_logic', 'comment': 'Reset polarity', 'def_val': ''}
Moving to VhdlEntityParserState.ENTITY
Moving to VhdlEntityParserState.PORTS
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Clock and Asynchronous reset'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'clk_sys', 'type': 'std_logic', 'comment': 'System clock', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'res_n', 'type': 'std_logic', 'comment': 'Asynchronous reset', 'direction': 'in'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Memory registers Interface'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'drv_bus', 'type': 'std_logic_vector (1023 downto 0)', 'comment': 'Driving bus', 'direction': 'in'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Protocol Control Interface'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'arbitration_lost', 'type': 'std_logic', 'comment': 'Arbitration lost', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'set_transmitter', 'type': 'std_logic', 'comment': 'Set unit to be transmitter (in SOF)', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'set_receiver', 'type': 'std_logic', 'comment': 'Set unit to be receiver', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'set_idle', 'type': 'std_logic', 'comment': 'Set unit to be idle', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'is_transmitter', 'type': 'std_logic', 'comment': 'Status outputs', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'is_receiver', 'type': 'std_logic', 'comment': 'Unit is receiver', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'is_idle', 'type': 'std_logic', 'comment': 'Unit is idle', 'direction': 'out'}
Moving to VhdlEntityParserState.ENTITY
Moving to VhdlEntityParserState.FINISH
********************************************************************************
Processing bit_stuffing entity
********************************************************************************
Moving to VhdlEntityParserState.ENTITY
Moving to VhdlEntityParserState.GENERICS
G_RESET_POLARITY
std_logic
'0'
Adding generic entry:  {'entry_type': 'generic', 'name': 'G_RESET_POLARITY', 'type': 'std_logic', 'comment': 'Reset polarity', 'def_val': "'0'"}
Moving to VhdlEntityParserState.ENTITY
Moving to VhdlEntityParserState.PORTS
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Clock and Asynchronous reset'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'clk_sys', 'type': 'std_logic', 'comment': 'System clock', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'res_n', 'type': 'std_logic', 'comment': 'Asynchronous reset', 'direction': 'in'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Data-path'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'data_in', 'type': 'std_logic', 'comment': 'Data Input (from Protocol Control)', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'data_out', 'type': 'std_logic', 'comment': 'Data Output (to CAN Bus)', 'direction': 'out'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Control signals'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'bst_trigger', 'type': 'std_logic', 'comment': 'Bit Stuffing Trigger (in SYNC segment)', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'stuff_enable', 'type': 'std_logic', 'comment': 'Bit Stuffing enabled. If not, data are only passed to the output', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'fixed_stuff', 'type': 'std_logic', 'comment': 'Bit Stuffing type (0-Normal, 1-Fixed)', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'stuff_length', 'type': 'std_logic_vector (2 downto 0)', 'comment': 'Length of Bit Stuffing rule', 'direction': 'in'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Status signals'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'bst_ctr', 'type': 'natural range 0 to 7', 'comment': 'Number of stuffed bits with Normal Bit stuffing', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'data_halt', 'type': 'std_logic', 'comment': 'Stuff bit is inserted, Protocol control operation to be halted forone bit time', 'direction': 'out'}
Moving to VhdlEntityParserState.ENTITY
Moving to VhdlEntityParserState.FINISH
********************************************************************************
Processing bit_destuffing entity
********************************************************************************
Moving to VhdlEntityParserState.ENTITY
Moving to VhdlEntityParserState.GENERICS
G_RESET_POLARITY
std_logic
'0'
Adding generic entry:  {'entry_type': 'generic', 'name': 'G_RESET_POLARITY', 'type': 'std_logic', 'comment': 'Reset polarity', 'def_val': "'0'"}
Moving to VhdlEntityParserState.ENTITY
Moving to VhdlEntityParserState.PORTS
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Clock and Asynchronous reset'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'clk_sys', 'type': 'in std_logic', 'comment': 'System clock', 'direction': ''}
Adding port entry:  {'entry_type': 'port', 'name': 'res_n', 'type': 'in std_logic', 'comment': 'Asynchronous reset', 'direction': ''}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Data-path'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'data_in', 'type': 'in std_logic', 'comment': 'Data input (from Bus Sampling)', 'direction': ''}
Adding port entry:  {'entry_type': 'port', 'name': 'data_out', 'type': 'out std_logic', 'comment': 'Data output (to Protocol Control)', 'direction': ''}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Control signals'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'bds_trigger', 'type': 'in std_logic', 'comment': 'Bit Destuffing Trigger (in Sample point, from Prescaler).', 'direction': ''}
Adding port entry:  {'entry_type': 'port', 'name': 'destuff_enable', 'type': 'in  std_logic', 'comment': 'Bit Destuffing is enabled.', 'direction': ''}
Adding port entry:  {'entry_type': 'port', 'name': 'stuff_error_enable', 'type': 'in  std_logic', 'comment': 'Stuff error detection enabled.', 'direction': ''}
Adding port entry:  {'entry_type': 'port', 'name': 'fixed_stuff', 'type': 'in  std_logic', 'comment': 'Bit destuffing type (0-Normal, 1-Fixed)', 'direction': ''}
Adding port entry:  {'entry_type': 'port', 'name': 'destuff_length', 'type': 'in  std_logic_vector (2 downto 0)', 'comment': 'Length of Bit De-Stuffing rule', 'direction': ''}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Status Outpus'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'stuff_error', 'type': 'out std_logic', 'comment': 'Stuff error detected (more equal consecutive bits than length ofstuff rule.', 'direction': ''}
Adding port entry:  {'entry_type': 'port', 'name': 'destuffed', 'type': 'out std_logic', 'comment': 'Data output is not valid, actual bit is stuff bit.', 'direction': ''}
Adding port entry:  {'entry_type': 'port', 'name': 'dst_ctr', 'type': 'out natural range 0 to 7', 'comment': 'Number of de-stuffed bits with normal bit stuffing method', 'direction': ''}
Moving to VhdlEntityParserState.ENTITY
Moving to VhdlEntityParserState.FINISH
********************************************************************************
Processing can_crc entity
********************************************************************************
Moving to VhdlEntityParserState.ENTITY
Moving to VhdlEntityParserState.GENERICS
G_RESET_POLARITY
std_logic
'0'
Adding generic entry:  {'entry_type': 'generic', 'name': 'G_RESET_POLARITY', 'type': 'std_logic', 'comment': 'Reset polarity', 'def_val': "'0'"}
G_CRC15_POL
std_logic_vector
x"C599"
Adding generic entry:  {'entry_type': 'generic', 'name': 'G_CRC15_POL', 'type': 'std_logic_vector', 'comment': 'CRC 15 polynomial', 'def_val': 'x"C599"'}
G_CRC17_POL
std_logic_vector
x"3685B"
Adding generic entry:  {'entry_type': 'generic', 'name': 'G_CRC17_POL', 'type': 'std_logic_vector', 'comment': 'CRC 17 polynomial', 'def_val': 'x"3685B"'}
G_CRC21_POL
std_logic_vector
x"302899"
Adding generic entry:  {'entry_type': 'generic', 'name': 'G_CRC21_POL', 'type': 'std_logic_vector', 'comment': 'CRC 15 polynomial', 'def_val': 'x"302899"'}
Moving to VhdlEntityParserState.ENTITY
Moving to VhdlEntityParserState.PORTS
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'System clock and Asynchronous Reset'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'clk_sys', 'type': 'std_logic', 'comment': 'System clock', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'res_n', 'type': 'std_logic', 'comment': 'Asynchronous reset', 'direction': 'in'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Memory registers interface'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'drv_bus', 'type': 'std_logic_vector (1023 downto 0)', 'comment': 'Driving bus', 'direction': 'in'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Data inputs for CRC calculation'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'data_tx_wbs', 'type': 'std_logic', 'comment': 'TX Data with Bit Stuffing', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'data_tx_nbs', 'type': 'std_logic', 'comment': 'TX Data without Bit Stuffing', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'data_rx_wbs', 'type': 'std_logic', 'comment': 'RX Data with Bit Stuffing', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'data_rx_nbs', 'type': 'std_logic', 'comment': 'RX Data without Bit Stuffing', 'direction': 'in'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Trigger signals to process the data on each CRC input.'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'trig_tx_wbs', 'type': 'std_logic', 'comment': 'Trigger for TX Data with Bit Stuffing', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'trig_tx_nbs', 'type': 'std_logic', 'comment': 'Trigger for TX Data without Bit Stuffing', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'trig_rx_wbs', 'type': 'std_logic', 'comment': 'Trigger for RX Data with Bit Stuffing', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'trig_rx_nbs', 'type': 'std_logic', 'comment': 'Trigger for RX Data without Bit Stuffing', 'direction': 'in'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Control signals'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'crc_enable', 'type': 'std_logic', 'comment': 'Enable for all CRC circuits.', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'crc_spec_enable', 'type': 'std_logic', 'comment': 'CRC calculation - speculative enable', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'is_receiver', 'type': 'std_logic', 'comment': 'Unit is receiver of a frame', 'direction': 'in'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'CRC Outputs'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'crc_15', 'type': 'std_logic_vector (14 downto 0)', 'comment': 'Calculated CRC 15', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'crc_17', 'type': 'std_logic_vector (16 downto 0)', 'comment': 'Calculated CRC 17', 'direction': 'out'}
Adding port entry:  {'entry_type': 'port', 'name': 'crc_21', 'type': 'std_logic_vector (20 downto 0)', 'comment': 'Calculated CRC 21', 'direction': 'out'}
Moving to VhdlEntityParserState.ENTITY
Moving to VhdlEntityParserState.FINISH
********************************************************************************
Processing prescaler entity
********************************************************************************
Moving to VhdlEntityParserState.ENTITY
Moving to VhdlEntityParserState.GENERICS
G_RESET_POLARITY
std_logic
'0'
Adding generic entry:  {'entry_type': 'generic', 'name': 'G_RESET_POLARITY', 'type': 'std_logic', 'comment': 'Reset polarity', 'def_val': "'0'"}
G_TSEG1_NBT_WIDTH
natural
8
Adding generic entry:  {'entry_type': 'generic', 'name': 'G_TSEG1_NBT_WIDTH', 'type': 'natural', 'comment': 'TSEG1 Width - Nominal Bit Time', 'def_val': '8'}
G_TSEG2_NBT_WIDTH
natural
8
Adding generic entry:  {'entry_type': 'generic', 'name': 'G_TSEG2_NBT_WIDTH', 'type': 'natural', 'comment': 'TSEG2 Width - Nominal Bit Time', 'def_val': '8'}
G_BRP_NBT_WIDTH
natural
8
Adding generic entry:  {'entry_type': 'generic', 'name': 'G_BRP_NBT_WIDTH', 'type': 'natural', 'comment': 'Baud rate prescaler Width - Nominal Bit Time', 'def_val': '8'}
G_SJW_NBT_WIDTH
natural
5
Adding generic entry:  {'entry_type': 'generic', 'name': 'G_SJW_NBT_WIDTH', 'type': 'natural', 'comment': 'Synchronisation Jump width Width - Nominal Bit Time', 'def_val': '5'}
G_TSEG1_DBT_WIDTH
natural
8
Adding generic entry:  {'entry_type': 'generic', 'name': 'G_TSEG1_DBT_WIDTH', 'type': 'natural', 'comment': 'TSEG1 Width - Data Bit Time', 'def_val': '8'}
G_TSEG2_DBT_WIDTH
natural
8
Adding generic entry:  {'entry_type': 'generic', 'name': 'G_TSEG2_DBT_WIDTH', 'type': 'natural', 'comment': 'TSEG2 Width - Data Bit Time', 'def_val': '8'}
G_BRP_DBT_WIDTH
natural
8
Adding generic entry:  {'entry_type': 'generic', 'name': 'G_BRP_DBT_WIDTH', 'type': 'natural', 'comment': 'Baud rate prescaler width - Data Bit Time', 'def_val': '8'}
G_SJW_DBT_WIDTH
natural
5
Adding generic entry:  {'entry_type': 'generic', 'name': 'G_SJW_DBT_WIDTH', 'type': 'natural', 'comment': 'Synchronisation Jump Width width - Data Bit Time', 'def_val': '5'}
G_SAMPLE_TRIGGER_COUNT
natural range 2 to 8
2
Adding generic entry:  {'entry_type': 'generic', 'name': 'G_SAMPLE_TRIGGER_COUNT', 'type': 'natural range 2 to 8', 'comment': 'Number of signals in Sample trigger', 'def_val': '2'}
Moving to VhdlEntityParserState.ENTITY
Moving to VhdlEntityParserState.PORTS
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Clock and Asynchronous reset'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'clk_sys', 'type': 'std_logic', 'comment': 'System clock', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'res_n', 'type': 'std_logic', 'comment': 'Asynchronous reset', 'direction': 'in'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Memory registers interface'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'drv_bus', 'type': 'std_logic_vector (1023 downto 0)', 'comment': 'Driving Bus', 'direction': 'in'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Control Interface'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'sync_edge', 'type': 'std_logic', 'comment': 'Synchronisation edge (from Bus sampling)', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'sp_control', 'type': 'std_logic_vector (1 downto 0)', 'comment': 'Sample control (Nominal, Data, Secondary)', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'sync_control', 'type': 'std_logic_vector (1 downto 0)', 'comment': 'Synchronisation control (No synchronisation, Hard Synchronisation,Resynchronisation', 'direction': 'in'}
Adding port entry:  {'entry_type': 'port', 'name': 'no_pos_resync', 'type': 'std_logic', 'comment': 'No re-synchronisation should be executed due to positive phaseerror', 'direction': 'in'}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Trigger signals'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'rx_triggers', 'type': 'out std_logic_vector (G_SAMPLE_TRIGGER_COUNT - 1 downto 0)', 'comment': 'RX Triggers', 'direction': ''}
Adding port entry:  {'entry_type': 'port', 'name': 'tx_trigger', 'type': 'out std_logic', 'comment': 'TX Trigger', 'direction': ''}
Moving to VhdlEntityParserState.SECTION
Adding section entry:  {'entry_type': 'section', 'comment': 'Status outputs'}
Moving to VhdlEntityParserState.PORTS
Adding port entry:  {'entry_type': 'port', 'name': 'time_quanta_clk', 'type': 'out std_logic', 'comment': 'Time quanta clock synchronisation output (debug only)', 'direction': ''}
Adding port entry:  {'entry_type': 'port', 'name': 'bt_fsm', 'type': 'out t_bit_time', 'comment': 'Bit Time FSM state', 'direction': ''}
Moving to VhdlEntityParserState.ENTITY
Moving to VhdlEntityParserState.FINISH
********************************************************************************
Processing bus_sampling entity
********************************************************************************
********************************************************************************
**  Finished
********************************************************************************
