@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":21:13:21:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":61:13:61:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":88:13:88:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":118:13:118:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":168:13:168:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":213:13:213:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":232:13:232:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":281:13:281:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":335:13:335:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":657:13:657:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":761:13:761:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":795:13:795:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":1059:13:1059:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":1369:13:1369:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":1396:13:1396:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":1441:13:1441:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":1474:13:1474:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":1492:13:1492:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":1518:13:1518:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":1559:13:1559:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":1581:13:1581:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":1599:13:1599:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":1616:13:1616:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":1635:13:1635:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":1652:13:1652:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":1681:13:1681:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":1712:13:1712:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":1802:13:1802:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":2026:13:2026:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":2187:13:2187:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":2203:13:2203:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":2219:13:2219:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":2235:13:2235:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":2267:13:2267:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":2648:13:2648:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":3661:13:3661:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":3732:13:3732:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":3861:13:3861:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":3879:13:3879:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":3896:13:3896:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":3911:13:3911:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":3926:13:3926:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":3953:13:3953:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":4065:13:4065:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":4096:13:4096:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":4142:13:4142:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":4252:13:4252:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":4436:13:4436:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":4477:13:4477:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":4503:13:4503:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":4520:13:4520:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":4597:13:4597:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":5361:13:5361:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":6171:13:6171:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":6280:13:6280:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":6318:13:6318:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":6391:13:6391:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":7280:13:7280:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":8337:13:8337:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":9296:13:9296:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":10032:13:10032:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":10747:13:10747:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":10781:13:10781:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":10817:13:10817:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":10864:13:10864:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":10898:13:10898:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":11764:13:11764:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":12807:13:12807:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":12819:15:12819:27|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":12830:13:12830:25|User defined pragma syn_black_box detected
@W: CG100 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v":12843:13:12843:25|User defined pragma syn_black_box detected
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_reg.vhd":76:15:76:21|Input port bits 15 to 12 of data_in(15 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_reg.vhd":76:15:76:21|Input port bits 15 to 12 of data_in(15 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_reg.vhd":76:15:76:21|Input port bits 31 to 11 of data_in(31 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_reg.vhd":76:15:76:21|Input port bit 0 of data_in(31 downto 0) is unused 
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_reg.vhd":79:15:79:18|Input port bits 3 to 2 of w_be(3 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_reg.vhd":76:15:76:21|Input port bits 15 to 12 of data_in(15 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_reg.vhd":76:15:76:21|Input port bit 18 of data_in(31 downto 0) is unused 
@W: CL247 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_reg.vhd":76:15:76:21|Input port bit 12 of data_in(31 downto 0) is unused 
@W: CL247 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_reg.vhd":76:15:76:21|Input port bit 6 of data_in(31 downto 0) is unused 
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_reg.vhd":76:15:76:21|Input port bits 31 to 13 of data_in(31 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_reg.vhd":79:15:79:18|Input port bits 3 to 2 of w_be(3 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_reg.vhd":76:15:76:21|Input port bits 31 to 29 of data_in(31 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_reg.vhd":76:15:76:21|Input port bits 7 to 1 of data_in(7 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_reg.vhd":76:15:76:21|Input port bits 7 to 3 of data_in(15 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_reg.vhd":76:15:76:21|Input port bit 31 of data_in(31 downto 0) is unused 
@W: CL247 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_reg.vhd":76:15:76:21|Input port bit 27 of data_in(31 downto 0) is unused 
@W: CL247 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_reg.vhd":76:15:76:21|Input port bit 23 of data_in(31 downto 0) is unused 
@W: CL247 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_reg.vhd":76:15:76:21|Input port bit 19 of data_in(31 downto 0) is unused 
@W: CL247 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_reg.vhd":76:15:76:21|Input port bit 15 of data_in(31 downto 0) is unused 
@W: CL247 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_reg.vhd":76:15:76:21|Input port bit 11 of data_in(31 downto 0) is unused 
@W: CL247 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_reg.vhd":76:15:76:21|Input port bit 7 of data_in(31 downto 0) is unused 
@W: CL247 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_reg.vhd":76:15:76:21|Input port bit 3 of data_in(31 downto 0) is unused 
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_reg.vhd":76:15:76:21|Input port bits 15 to 10 of data_in(15 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/control_registers_reg_map.vhd":97:11:97:17|Input port bits 15 to 8 of address(15 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/control_registers_reg_map.vhd":97:11:97:17|Input port bits 1 to 0 of address(15 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_reg.vhd":76:15:76:21|Input port bits 31 to 2 of data_in(31 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_reg.vhd":79:15:79:18|Input port bits 3 to 1 of w_be(3 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_reg.vhd":76:15:76:21|Input port bits 31 to 20 of data_in(31 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_reg.vhd":79:15:79:18|Input port bit 3 of w_be(3 downto 0) is unused 
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/test_registers_reg_map.vhd":92:11:92:17|Input port bits 15 to 8 of address(15 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/test_registers_reg_map.vhd":92:11:92:17|Input port bits 1 to 0 of address(15 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_registers.vhd":196:8:196:15|Input port bits 511 to 386 of stat_bus(511 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_registers.vhd":196:8:196:15|Input port bit 383 of stat_bus(511 downto 0) is unused 
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_registers.vhd":196:8:196:15|Input port bits 369 to 306 of stat_bus(511 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_registers.vhd":196:8:196:15|Input port bits 299 to 297 of stat_bus(511 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_registers.vhd":196:8:196:15|Input port bits 256 to 252 of stat_bus(511 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_registers.vhd":196:8:196:15|Input port bits 187 to 110 of stat_bus(511 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_registers.vhd":196:8:196:15|Input port bits 98 to 90 of stat_bus(511 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_registers.vhd":196:8:196:15|Input port bit 80 of stat_bus(511 downto 0) is unused 
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_registers.vhd":196:8:196:15|Input port bits 70 to 10 of stat_bus(511 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_registers.vhd":196:8:196:15|Input port bits 8 to 6 of stat_bus(511 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":114:8:114:13|Input port bits 11 to 7 of addr_a(11 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":129:8:129:13|Input port bits 11 to 7 of addr_b(11 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer_ram.vhd":130:8:130:25|Input port bits 63 to 52 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer_ram.vhd":130:8:130:25|Input port bits 47 to 44 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer_ram.vhd":130:8:130:25|Input port bits 31 to 2 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer.vhd":224:8:224:14|Input port bits 1023 to 477 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer.vhd":224:8:224:14|Input port bits 475 to 355 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer.vhd":224:8:224:14|Input port bits 349 to 0 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd":129:8:129:25|Input port bits 63 to 52 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd":129:8:129:25|Input port bits 47 to 37 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd":129:8:129:25|Input port bits 31 to 2 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer.vhd":150:8:150:24|Input port bits 7 to 1 of txtb_sw_cmd_index(7 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd":129:8:129:25|Input port bits 63 to 52 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd":129:8:129:25|Input port bits 47 to 37 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd":129:8:129:25|Input port bits 31 to 2 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer.vhd":150:8:150:24|Input port bits 7 to 2 of txtb_sw_cmd_index(7 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer.vhd":150:8:150:24|Input port bit 0 of txtb_sw_cmd_index(7 downto 0) is unused 
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd":129:8:129:25|Input port bits 63 to 52 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd":129:8:129:25|Input port bits 47 to 37 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd":129:8:129:25|Input port bits 31 to 2 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer.vhd":150:8:150:24|Input port bits 7 to 3 of txtb_sw_cmd_index(7 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer.vhd":150:8:150:24|Input port bits 1 to 0 of txtb_sw_cmd_index(7 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd":129:8:129:25|Input port bits 63 to 52 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd":129:8:129:25|Input port bits 47 to 37 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd":129:8:129:25|Input port bits 31 to 2 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer.vhd":150:8:150:24|Input port bits 7 to 4 of txtb_sw_cmd_index(7 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer.vhd":150:8:150:24|Input port bits 2 to 0 of txtb_sw_cmd_index(7 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd":129:8:129:25|Input port bits 63 to 52 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd":129:8:129:25|Input port bits 47 to 37 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd":129:8:129:25|Input port bits 31 to 2 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer.vhd":150:8:150:24|Input port bits 7 to 5 of txtb_sw_cmd_index(7 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer.vhd":150:8:150:24|Input port bits 3 to 0 of txtb_sw_cmd_index(7 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd":129:8:129:25|Input port bits 63 to 52 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd":129:8:129:25|Input port bits 47 to 37 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd":129:8:129:25|Input port bits 31 to 2 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer.vhd":150:8:150:24|Input port bits 7 to 6 of txtb_sw_cmd_index(7 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer.vhd":150:8:150:24|Input port bits 4 to 0 of txtb_sw_cmd_index(7 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd":129:8:129:25|Input port bits 63 to 52 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd":129:8:129:25|Input port bits 47 to 37 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd":129:8:129:25|Input port bits 31 to 2 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer.vhd":150:8:150:24|Input port bit 7 of txtb_sw_cmd_index(7 downto 0) is unused 
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer.vhd":150:8:150:24|Input port bits 5 to 0 of txtb_sw_cmd_index(7 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd":129:8:129:25|Input port bits 63 to 52 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd":129:8:129:25|Input port bits 47 to 37 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd":129:8:129:25|Input port bits 31 to 2 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer.vhd":150:8:150:24|Input port bits 6 to 0 of txtb_sw_cmd_index(7 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_arbitrator_fsm.vhd":128:8:128:18|Input port bits 5 to 2 of txtb_hw_cmd(5 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_arbitrator.vhd":125:8:125:20|Input port bit 7 of txtb_allow_bb(7 downto 0) is unused 
@W: CL247 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_arbitrator.vhd":125:8:125:20|Input port bit 5 of txtb_allow_bb(7 downto 0) is unused 
@W: CL247 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_arbitrator.vhd":125:8:125:20|Input port bit 3 of txtb_allow_bb(7 downto 0) is unused 
@W: CL247 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_arbitrator.vhd":125:8:125:20|Input port bit 1 of txtb_allow_bb(7 downto 0) is unused 
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_arbitrator.vhd":200:8:200:14|Input port bits 1023 to 477 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_arbitrator.vhd":200:8:200:14|Input port bits 474 to 473 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_arbitrator.vhd":200:8:200:14|Input port bits 471 to 0 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/frame_filters.vhd":129:8:129:14|Input port bits 1023 to 331 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/frame_filters.vhd":129:8:129:14|Input port bits 80 to 0 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/int_manager.vhd":157:8:157:14|Input port bits 1023 to 876 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/int_manager.vhd":157:8:157:14|Input port bits 863 to 844 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/int_manager.vhd":157:8:157:14|Input port bits 831 to 812 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/int_manager.vhd":157:8:157:14|Input port bits 799 to 780 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/int_manager.vhd":157:8:157:14|Input port bits 767 to 748 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/int_manager.vhd":157:8:157:14|Input port bits 735 to 0 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/shift_reg_byte.vhd":117:8:117:21|Input port bit 0 of byte_input_sel(3 downto 0) is unused 
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/protocol_control.vhd":128:8:128:14|Input port bits 1023 to 514 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/protocol_control.vhd":128:8:128:14|Input port bits 506 to 478 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/protocol_control.vhd":128:8:128:14|Input port bits 476 to 472 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/protocol_control.vhd":128:8:128:14|Input port bits 464 to 461 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/protocol_control.vhd":128:8:128:14|Input port bits 459 to 430 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/protocol_control.vhd":128:8:128:14|Input port bits 428 to 375 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/protocol_control.vhd":128:8:128:14|Input port bits 372 to 0 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/fault_confinement.vhd":114:8:114:14|Input port bits 1023 to 514 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/fault_confinement.vhd":114:8:114:14|Input port bits 512 to 510 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/fault_confinement.vhd":114:8:114:14|Input port bits 508 to 427 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/fault_confinement.vhd":114:8:114:14|Input port bits 399 to 0 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_crc.vhd":129:8:129:14|Input port bits 1023 to 511 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_crc.vhd":129:8:129:14|Input port bits 509 to 0 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_time_cfg_capture.vhd":136:8:136:14|Input port bits 1023 to 510 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_time_cfg_capture.vhd":136:8:136:14|Input port bits 508 to 61 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bus_sampling.vhd":145:8:145:14|Input port bits 1023 to 510 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bus_sampling.vhd":145:8:145:14|Input port bits 508 to 383 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bus_sampling.vhd":145:8:145:14|Input port bits 372 to 0 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.

