@W: FA239 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer.vhd":628:17:628:22|ROM rx_buffer_inst.rwcnt_com[4:0] (in view: ctu_can_fd_rtl.can_top_level(rtl)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer.vhd":628:17:628:22|ROM rx_buffer_inst.rwcnt_com[4:0] (in view: ctu_can_fd_rtl.can_top_level(rtl)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FX107 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":143:11:143:20|RAM rx_buffer_inst.rx_buffer_ram_inst.rx_buf_RAM_inst.ram_memory_3[31:0] (in view: ctu_can_fd_rtl.can_top_level(rtl)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W: FX107 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":143:11:143:20|RAM txt_buf_comp_gen\.1\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_3[0:7] (in view: ctu_can_fd_rtl.can_top_level(rtl)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W: FX107 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":143:11:143:20|RAM txt_buf_comp_gen\.1\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_2[0:7] (in view: ctu_can_fd_rtl.can_top_level(rtl)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W: FX107 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":143:11:143:20|RAM txt_buf_comp_gen\.1\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_1[0:7] (in view: ctu_can_fd_rtl.can_top_level(rtl)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W: FX107 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":143:11:143:20|RAM txt_buf_comp_gen\.1\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory[0:7] (in view: ctu_can_fd_rtl.can_top_level(rtl)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W: FX107 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":143:11:143:20|RAM txt_buf_comp_gen\.0\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_3[0:7] (in view: ctu_can_fd_rtl.can_top_level(rtl)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W: FX107 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":143:11:143:20|RAM txt_buf_comp_gen\.0\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_2[0:7] (in view: ctu_can_fd_rtl.can_top_level(rtl)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W: FX107 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":143:11:143:20|RAM txt_buf_comp_gen\.0\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_1[0:7] (in view: ctu_can_fd_rtl.can_top_level(rtl)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W: FX107 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":143:11:143:20|RAM txt_buf_comp_gen\.0\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory[0:7] (in view: ctu_can_fd_rtl.can_top_level(rtl)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W: FX107 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":143:11:143:20|RAM txt_buf_comp_gen\.2\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_3[0:7] (in view: ctu_can_fd_rtl.can_top_level(rtl)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W: FX107 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":143:11:143:20|RAM txt_buf_comp_gen\.2\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_2[0:7] (in view: ctu_can_fd_rtl.can_top_level(rtl)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W: FX107 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":143:11:143:20|RAM txt_buf_comp_gen\.2\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_1[0:7] (in view: ctu_can_fd_rtl.can_top_level(rtl)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W: FX107 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":143:11:143:20|RAM txt_buf_comp_gen\.2\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory[0:7] (in view: ctu_can_fd_rtl.can_top_level(rtl)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W: FX107 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":143:11:143:20|RAM txt_buf_comp_gen\.3\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_3[0:7] (in view: ctu_can_fd_rtl.can_top_level(rtl)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W: FX107 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":143:11:143:20|RAM txt_buf_comp_gen\.3\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_2[0:7] (in view: ctu_can_fd_rtl.can_top_level(rtl)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W: FX107 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":143:11:143:20|RAM txt_buf_comp_gen\.3\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_1[0:7] (in view: ctu_can_fd_rtl.can_top_level(rtl)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W: FX107 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":143:11:143:20|RAM txt_buf_comp_gen\.3\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory[0:7] (in view: ctu_can_fd_rtl.can_top_level(rtl)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W: MO160 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_registers.vhd":763:8:763:9|Register bit memory_registers_inst.tx_double_parity_error (in view view:ctu_can_fd_rtl.can_top_level(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_registers.vhd":763:8:763:9|Register bit memory_registers_inst.tx_parity_error (in view view:ctu_can_fd_rtl.can_top_level(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_arbitrator.vhd":761:4:761:5|Register bit tx_arbitrator_inst.txtb_pointer_meta_q[3] (in view view:ctu_can_fd_rtl.can_top_level(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: BN132 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_arbitrator.vhd":761:4:761:5|Removing instance tx_arbitrator_inst.txtb_pointer_meta_q[4] because it is equivalent to instance tx_arbitrator_inst.txtb_pointer_meta_q[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: MO160 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_fsm.vhd":402:8:402:9|Register bit curr_state[0] (in view view:ctu_can_fd_rtl.txt_buffer_fsm_3(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_fsm.vhd":402:8:402:9|Register bit curr_state[0] (in view view:ctu_can_fd_rtl.txt_buffer_fsm_2(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_fsm.vhd":402:8:402:9|Register bit curr_state[0] (in view view:ctu_can_fd_rtl.txt_buffer_fsm_0(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_fsm.vhd":402:8:402:9|Register bit curr_state[0] (in view view:ctu_can_fd_rtl.txt_buffer_fsm_1(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_time_cfg_capture.vhd":284:8:284:9|Register bit bit_time_cfg_capture_inst.tseg1_dbt[7] (in view view:ctu_can_fd_rtl.prescaler_8_8_8_5_8_8_8_5_2(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: BN132 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/dff_arst.vhd":106:8:106:9|Removing instance can_core_inst.fault_confinement_inst.fault_confinement_fsm_inst.dff_fc_reset_inst.output because it is equivalent to instance prescaler_inst.bit_time_cfg_capture_inst.drv_ena_reg. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/dff_arst.vhd":106:8:106:9|Removing instance can_core_inst.trigger_mux_inst.crc_trig_tx_wbs_reg.output because it is equivalent to instance bus_sampling_inst.tx_trigger_reg_inst.output. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BW110 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_top_level.vhd":103:7:103:19|Renaming port can_top_level due to collision with Verilog/ System Verilog reserved word 
@W: BW156 :|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
@W: MT420 |Found inferred clock can_top_level|clk_sys with period 10.00ns. Please declare a user-defined clock on port clk_sys.
