@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
@N: MO106 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer.vhd":628:17:628:22|Found ROM rx_buffer_inst.rwcnt_com[4:0] (in view: ctu_can_fd_rtl.can_top_level(rtl)) with 16 words by 5 bits.
@N: FX403 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":143:11:143:20|Property "block_ram" or "no_rw_check" found for RAM rx_buffer_inst.rx_buffer_ram_inst.rx_buf_RAM_inst.ram_memory_3[31:0] with specified coding style. Inferring block RAM.
@N: FX702 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":143:11:143:20|Found startup values on RAM instance rx_buffer_inst.rx_buffer_ram_inst.rx_buf_RAM_inst.ram_memory_3[31:0] (in view: ctu_can_fd_rtl.can_top_level(rtl)).
@N: FX702 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":143:11:143:20|Found startup values on RAM instance rx_buffer_inst.rx_buffer_ram_inst.rx_buf_RAM_inst.ram_memory_3[31:0]
@N: FX403 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":143:11:143:20|Property "block_ram" or "no_rw_check" found for RAM txt_buf_comp_gen\.1\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_3[0:7] with specified coding style. Inferring block RAM.
@N: FX403 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":143:11:143:20|Property "block_ram" or "no_rw_check" found for RAM txt_buf_comp_gen\.1\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_2[0:7] with specified coding style. Inferring block RAM.
@N: FX403 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":143:11:143:20|Property "block_ram" or "no_rw_check" found for RAM txt_buf_comp_gen\.1\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_1[0:7] with specified coding style. Inferring block RAM.
@N: FX403 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":143:11:143:20|Property "block_ram" or "no_rw_check" found for RAM txt_buf_comp_gen\.1\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory[0:7] with specified coding style. Inferring block RAM.
@N: FX403 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":143:11:143:20|Property "block_ram" or "no_rw_check" found for RAM txt_buf_comp_gen\.0\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_3[0:7] with specified coding style. Inferring block RAM.
@N: FX403 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":143:11:143:20|Property "block_ram" or "no_rw_check" found for RAM txt_buf_comp_gen\.0\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_2[0:7] with specified coding style. Inferring block RAM.
@N: FX403 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":143:11:143:20|Property "block_ram" or "no_rw_check" found for RAM txt_buf_comp_gen\.0\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_1[0:7] with specified coding style. Inferring block RAM.
@N: FX403 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":143:11:143:20|Property "block_ram" or "no_rw_check" found for RAM txt_buf_comp_gen\.0\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory[0:7] with specified coding style. Inferring block RAM.
@N: FX403 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":143:11:143:20|Property "block_ram" or "no_rw_check" found for RAM txt_buf_comp_gen\.2\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_3[0:7] with specified coding style. Inferring block RAM.
@N: FX403 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":143:11:143:20|Property "block_ram" or "no_rw_check" found for RAM txt_buf_comp_gen\.2\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_2[0:7] with specified coding style. Inferring block RAM.
@N: FX403 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":143:11:143:20|Property "block_ram" or "no_rw_check" found for RAM txt_buf_comp_gen\.2\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_1[0:7] with specified coding style. Inferring block RAM.
@N: FX403 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":143:11:143:20|Property "block_ram" or "no_rw_check" found for RAM txt_buf_comp_gen\.2\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory[0:7] with specified coding style. Inferring block RAM.
@N: FX403 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":143:11:143:20|Property "block_ram" or "no_rw_check" found for RAM txt_buf_comp_gen\.3\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_3[0:7] with specified coding style. Inferring block RAM.
@N: FX403 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":143:11:143:20|Property "block_ram" or "no_rw_check" found for RAM txt_buf_comp_gen\.3\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_2[0:7] with specified coding style. Inferring block RAM.
@N: FX403 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":143:11:143:20|Property "block_ram" or "no_rw_check" found for RAM txt_buf_comp_gen\.3\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_1[0:7] with specified coding style. Inferring block RAM.
@N: FX403 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":143:11:143:20|Property "block_ram" or "no_rw_check" found for RAM txt_buf_comp_gen\.3\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory[0:7] with specified coding style. Inferring block RAM.
@N: MO231 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer_pointers.vhd":285:8:285:9|Found counter in view:ctu_can_fd_rtl.can_top_level(rtl) instance rx_buffer_inst.rx_buffer_pointers_inst.write_pointer_raw_i[4:0] 
@N: MO231 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer_pointers.vhd":308:8:308:9|Found counter in view:ctu_can_fd_rtl.can_top_level(rtl) instance rx_buffer_inst.rx_buffer_pointers_inst.write_pointer_ts_i[4:0] 
@N: MO231 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer.vhd":699:8:699:9|Found counter in view:ctu_can_fd_rtl.can_top_level(rtl) instance rx_buffer_inst.read_counter_q[4:0] 
@N: MF179 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_arbitrator.vhd":356:14:356:48|Found 32 by 32 bit equality operator ('==') tx_arbitrator_inst.less_than\.un6_timestamp_valid (in view: ctu_can_fd_rtl.can_top_level(rtl))
@N: MO231 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/control_counter.vhd":230:8:230:9|Found counter in view:ctu_can_fd_rtl.control_counter_9(rtl) instance compl_ctr_q[8:0] 
@N: MO231 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/control_counter.vhd":202:8:202:9|Found counter in view:ctu_can_fd_rtl.control_counter_9(rtl) instance ctrl_ctr_q[8:0] 
@N: MF179 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/err_detector.vhd":326:27:326:44|Found 15 by 15 bit equality operator ('==') crc_15_ok (in view: ctu_can_fd_rtl.err_detector_true(rtl))
@N: MF179 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/err_detector.vhd":330:27:330:44|Found 17 by 17 bit equality operator ('==') crc_17_ok (in view: ctu_can_fd_rtl.err_detector_true(rtl))
@N: MF179 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/err_detector.vhd":334:27:334:44|Found 21 by 21 bit equality operator ('==') crc_21_ok (in view: ctu_can_fd_rtl.err_detector_true(rtl))
@N: MO231 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/reintegration_counter.vhd":154:8:154:9|Found counter in view:ctu_can_fd_rtl.reintegration_counter(rtl) instance reinteg_ctr_q[8:0] 
@N: MO225 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/operation_control.vhd":227:8:227:9|There are no possible illegal states for state machine curr_state[0:3] (in view: ctu_can_fd_rtl.operation_control(rtl)); safe FSM implementation is not required.
@N: MO231 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_time_counters.vhd":192:8:192:9|Found counter in view:ctu_can_fd_rtl.bit_time_counters_9_8_1(rtl) instance tq_counter_q[7:0] 
@N: MO231 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_time_counters.vhd":223:8:223:9|Found counter in view:ctu_can_fd_rtl.bit_time_counters_9_8_1(rtl) instance segm_counter_q[8:0] 
@N: MO231 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_time_counters.vhd":192:8:192:9|Found counter in view:ctu_can_fd_rtl.bit_time_counters_9_8_0(rtl) instance tq_counter_q[7:0] 
@N: MO231 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_time_counters.vhd":223:8:223:9|Found counter in view:ctu_can_fd_rtl.bit_time_counters_9_8_0(rtl) instance segm_counter_q[8:0] 
@N: MF135 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_data_cache.vhd":189:8:189:9|RAM tx_data_cache_inst.tx_cache (in view: ctu_can_fd_rtl.bus_sampling_255_8_7_8_true_15(rtl)) is 8 words by 1 bits.
@N: MO231 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/ssp_generator.vhd":213:8:213:9|Found counter in view:ctu_can_fd_rtl.ssp_generator_15(rtl) instance btmc_q[14:0] 
@N: FX271 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/trigger_generator.vhd":196:8:196:9|Replicating instance prescaler_inst.trigger_generator_inst.rx_trig_req_q (in view: ctu_can_fd_rtl.can_top_level(rtl)) with 6 loads 1 time to improve timing.
@N: FX271 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_time_fsm.vhd":208:8:208:9|Replicating instance prescaler_inst.bit_time_fsm_inst.current_state[0] (in view: ctu_can_fd_rtl.can_top_level(rtl)) with 35 loads 2 times to improve timing.
@N: FX271 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/segment_end_detector.vhd":293:19:294:37|Replicating instance prescaler_inst.segment_end_detector_inst.un1_h_sync_valid_i (in view: ctu_can_fd_rtl.can_top_level(rtl)) with 40 loads 2 times to improve timing.
@N: FX271 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/dff_arst_ce.vhd":109:8:109:9|Replicating instance can_core_inst.bit_destuffing_inst.dff_data_out_val_reg.output (in view: ctu_can_fd_rtl.can_top_level(rtl)) with 17 loads 1 time to improve timing.
@N: FX271 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/segment_end_detector.vhd":308:32:310:70|Replicating instance prescaler_inst.segment_end_detector_inst.un3_m10_0 (in view: ctu_can_fd_rtl.can_top_level(rtl)) with 46 loads 3 times to improve timing.
@N: FX271 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_reg.vhd":170:24:170:25|Replicating instance memory_registers_inst.control_registers_reg_map_comp.settings_reg_comp.reg_value_r[6] (in view: ctu_can_fd_rtl.can_top_level(rtl)) with 31 loads 1 time to improve timing.
@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
