@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
@N: MF104 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":85:7:85:21|Found compile point of type hard on View view:ctu_can_fd_rtl.inf_ram_wrapper_32_128_12_true_true(rtl) 
@N: MF105 |Performing bottom-up mapping of Compile point view:ctu_can_fd_rtl.inf_ram_wrapper_32_128_12_true_true(rtl) 
@N: MF106 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":85:7:85:21|Mapping Compile point view:ctu_can_fd_rtl.inf_ram_wrapper_32_128_12_true_true(rtl) because 
@N: MO106 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer.vhd":628:17:628:22|Found ROM can_top_level_inst.rx_buffer_inst.rwcnt_com[4:0] (in view: ctu_can_fd_rtl.ctu_can_fd_libero_top(rtl)) with 16 words by 5 bits.
@N: MT615 |Found clock SYS_CLK with period 10.00ns 
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
